Asymmetric transistor sizing targeting radiation-hardened circuits-Reference-Cited by-同舟云学术

Asymmetric transistor sizing targeting radiation-hardened circuits

Published:2011-06-15 Issue:1 Volume:94 Page:11-18
ISSN:0948-7921
Container-title:Electrical Engineering
language:en
Short-container-title:Electr Eng

Author:

Lazzari Cristiano,Wirth Gilson,Kastensmidt Fernanda Lima,Anghel Lorena,Reis Ricardo Augusto da Luz

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s00202-011-0212-8.pdf

Reference18 articles.

1. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43: 2874–2878

2. Rockett L (1988) An SEU hardened CMOS data latch design. IEEE Trans Nucl Sci NS-35(6): 1682–1687

3. Whitaker S, Canaris J, Liu K (1991) SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder. IEEE Trans Nucl Sci NS-36(6): 1471–1477

4. Mohanram K, Touba N (2003) Cost-effective approach for reducing soft error failure rate in logic circuits. In: Proceedings ITC, 2003, IEEE Computer Society, Los Alamitos

5. Nicolaidis M (1999) Time redundancy based soft-error tolerance to rescue nanometer technologies. In: Proceedings of 17th VLSI Test Symposium (VTS 99). IEEE Press, pp 86–94

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