Transistor-Level Radiation Hardening by Design Techniques in Complex Gates

Abstract

Single Event Transients (SETs) have become a major reliability concern for integrated circuits used in critical applications. Research to improve the radiation robustness of digital circuits has been conducted, assessing all abstraction levels (from the device up to the system). This study evaluates transistor-level radiation-hardened techniques in combinational logic, such as transistor folding, sizing and reordering. In addition, the efficiency of using supergates, including series-parallel and non-series-parallel CMOS structures, to harden the combinational logic is discussed. The dependence of input signals probability on a logic cell susceptibility to SET is assessed. Moreover, a new concept of electrical masking is introduced. The robustness of the investigated logic cells was evaluated regarding their SET rate. The CREME96 tool was used to generate the SET rates, and an electrical model was used to perform particle hit simulations. Obtained results have indicated that modifying the structure of logic gates can substantially improve circuit robustness without necessarily worsening its performance. Besides, using supergates in combinational logic design has demonstrated to be a promising hardening strategy. The most robust supergate implementation of a five-input logic function provided up to [Formula: see text] SET rate reduction regarding an approach based on standard cells, along with lower critical delay ([Formula: see text]) and average power ([Formula: see text]).