Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications-Reference-Cited by-同舟云学术

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Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications

Published:2019-11-20 Issue:11 Volume:27 Page:3995-4005
ISSN:0946-7076
Container-title:Microsystem Technologies
language:en
Short-container-title:Microsyst Technol

Author:

Basak A.,Chanda M.,Sarkar A.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s00542-019-04691-x.pdf

Reference42 articles.

1. Abadi RMI, Ziabari SAS (2016) Representation of type I hetero structure junctionless tunnel field effect transistor for high performance logic application. Appl Phys A 122:616

2. Arora ND, Rios R, Huang CL, Raol K (1994) PCIM: a physically based continuous short-channel IGFET model for circuit simulation. IEEE Trans Electron Devices 41(6):988–997

3. Bentrcia T, Djeffal F, Chebaki E (2017) Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodeling technique. IET Circuits Devices Syst 11(6):618–623

4. Biswas K, Sarkar A, Sarkar CK (2018) Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET. Micro Nano Lett 13(5):690–694

5. Chakraborty A, Sarkar A (2015) Investigation of analog/RF performance of staggered heterojunctions based nanowire tunnelling field-effect transistors. Superlattices Microstruct 80:125–135

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