Author:
Jegadheesan V.,Sivasankaran K.
Funder
Council of Scientific and Industrial Research, India
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Modelling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference30 articles.
1. Loubet, N., et al.: Stacked nanosheet gate-all around transistor to enable scaling beyond FinFET. In: Proceedings of IEEE Symposium on VLSI Technology Digest of Technical Papers (2017)
2. Lee, B.-H., Ahn, D.-C., Kang, M.-H., Jeon, S.-B., Choi, Y.-K.: Vertically integrated nanowire-based unified memory. Nano Lett. 16, 5909–5916 (2016)
3. Ernst, T., Dupré, C., Isheden, C., Bernard, E., et al.: Novel 3D integration process for highly scalable nano-beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack. In: IEDM (2006)
4. Fang, W.W., Singh, N., Bera, L.K., Nguyen, H.S., Rustagi, S.C., Lo, G.Q., Balasubramanian, N., Kwong, D.-L.: Vertically stacked SiGe nanowire array channel CMOS transistors. IEEE Electron Device Lett. 28, 211–213 (2007)
5. Bernard, E., Ernst, T., et al.: Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI. Solid-State Electron. 52, 1297–1302 (2008)
Cited by
10 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献