Analysis of DLL Jitter due to Voltage-Controlled Delay Line

Author:

Gholami Mohammad,Ardeshir Gholamreza

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 8 Channels 14 bits 100 MHz Sample and Hold Circuit Based on Delay-Locked Loop Control;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

2. Low power 10T phase and frequency detector for high frequency phase locked loop;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2023-06-02

3. A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop;Circuits, Systems, and Signal Processing;2019-09-04

4. Overview of Analog Wide Range Delay Locked Loops;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2018-11-07

5. Low-Power High-Frequency Phase Frequency Detector for Minimal Blind-Zone Phase-Locked Loops;Circuits, Systems, and Signal Processing;2018-06-23

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