Author:
Sofimowloodi Sobhan,Razaghian Farhad,Gholami Mohammad
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Reference14 articles.
1. R.J. Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design Layout and Simulation, IEEE Press Series on Microelectronics System (Wiley-IEEE Press, London, 2000), pp. 355–361 and 383–387
2. C.C. Chung, C.L. Chang, A wide-range all-digital delay-locked loop in 65 nm CMOS technology, in 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), pp. 66–69, 26 Apr 2010
3. X. Gao, E. Klumperink, G. Socci, M. Bohsali, B. Nauta, Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector. IEEE J. Solid-State Circuits 45(9), 1809–1821 (2010)
4. M. Gholami, G. Ardeshir, Analysis of DLL jitter due to voltage-controlled delay line. Circuits Syst. Signal Process. 32(5), 35–2119 (2013)
5. M. Gholami, Phase detector with minimal blind zone and reset time for GSamples/s DLLs. Circuits Syst Signal Process. 36, 3549–3563 (2017)
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