Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01695-7.pdf
Reference54 articles.
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3. Tayal S, Nandi A (2017) Study of 6T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET. Superlattices and Microstructures. https://doi.org/10.1016/j.spmi.2017.08.061
4. Ghosh P, Bhowmick B (2020) Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis. Int J RF Microw Comput Aided Eng. 30(e22269)
5. K. Baral, P.K. Singh, S. Kumar, S. Chander, S. Jit, Ultrathin body nanowire hetero dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability, Superlattice. Microst. 138 (2019), doi: https://doi.org/10.1016/j.spmi.2019.106364
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