Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s12633-019-00350-y.pdf
Reference25 articles.
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2. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-K gate dielectric. IEEE Trans Electron Devices 54:1725–1733
3. Singh A, Chaudhary SK, Panday CK, Sharma SM, Sarkar CK (2019) Design and analysis of High K Silicon Nano Tube Tunnel FET Device IET Circuit, Devices and Systems (Accepted). https://doi.org/10.1049/iet-cds.2019.0230
4. Harris H, Choi K, Mehta N, Chandolu A, Biswas N, Kipshidze G, Nikishin S, Gangopadhyay S (2002) HfO2 gate dielectric with 0.5 nm equivalent oxide thickness. Appl Phys Lett
5. Memisevic E, Svensson J, Hellenbrand M, Lind E, Wernersson L-E (2017) Vertical InAs/GaAsSb/GaSb Tunneling Field-Effect Transistor on Si with S = 48 mV/decade and Ion = 10μA/μm for Ioff = 1nA/μm at VDS = 0.3 V IEEE International Electron Devices Meeting, IEDM. 19.1.1–19.1.4
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