Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters-Reference-Cited by-同舟云学术

Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

Published:2020-02-13 Issue:1 Volume:13 Page:155-166
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Vanlalawmpuia K.^ORCID,Bhowmick Brinda

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1007/s12633-020-00411-7.pdf

Reference37 articles.

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2. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–2110

3. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–337

4. Villalon A, Carval GL, Martinie S, Royer CL, Jaud MA, Cristoloveanu S (2014) Further insights in TFET operation. IEEE Trans Electron Devices 61:2893–2898

5. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28:743–745

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