Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs-Reference-Cited by-同舟云学术

Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs

Published:2020-06-30 Issue:6 Volume:13 Page:1731-1739
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Singh Prince Kumar,Baral Kamalaksha,Kumar Sanjay,Tripathy Manas Ranjan,Singh Ashish Kumar,Upadhyay Rishibrind Kumar,Chander Sweta,Jit Satyabrata^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-020-00563-6.pdf

Reference29 articles.

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3. Dash S, Mishra GP (Oct. 2015) A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattice Microst 86:211–220

4. Kumar S, Goel E, Singh K, Singh B, Kumar M, Jit S (Aug. 2016) A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high- k stacked gate-oxide structure. IEEE Trans. Electron Devices 60(8):3291–3299

5. Kumar S, Singh K, Chander S, Goel E, Singh PK, Baral K, Singh B, Jit S (Jan. 2018) 2-D analytical drain current model of double-gate heterojunction TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans. Electron Devices 65(1):331–338

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