Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01392-x.pdf
Reference34 articles.
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2. Kobayashi M, Hiramoto T (2016) On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film. AIP Adv 6:025113. https://doi.org/10.1063/1.4942427
3. Kobayashi M (2018) A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor. Appl Phys Express 11:110101. https://doi.org/10.7567/apex.11.110101
4. Si M, Su C-J, Jiang C, Conrad NJ, Zhou H, Maize KD, Qiu G, Wu C-T, Shakouri A, Alam MA, Ye PD (2017) Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nature Nanotech 13:24–28. https://doi.org/10.1038/s41565-017-0010-1
5. Bal P, Akram MW, Mondal P, Ghosh B (2013) Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET). J Comput Electron 12:782–789. https://doi.org/10.1007/s10825-013-0483-6
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