The Study and Modeling of saturation drain voltage for junctionless FinFET-Reference-Cited by-同舟云学术

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The Study and Modeling of saturation drain voltage for junctionless FinFET

Published:2024-04 Issue: Volume:188 Page:207798
ISSN:2773-0123
Container-title:Micro and Nanostructures
language:en
Short-container-title:Micro and Nanostructures

Author:

Lou Haijun,Lei Qianjin,Yang Yumei,Lin Xinnan

Funder

National Natural Science Foundation of China

Anhui Polytechnic University

Publisher

Elsevier BV

Reference30 articles.

1. Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes;S,2017

2. Reliability characterization of 10nm FinFET technology with multi-VT gate stack for low power and high performance;Jin,2016

3. FinFETs and Other Multi-Gate Transistors;Colinge,2008

4. Properties of accumulation-mode multi-gate field-effect transistors;Colinge;Jpn. J. Appl. Phys.,2009

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