1. Takagi S, Tezuka T, Irisawa T, Nakaharai S, Numata T, Usuda K, Sugiyama N, Shichijo M, Nakane R, Sugahara S (2007) Device structures and carrier transport properties of advanced CMOS using high mobility channels. Solid State Electronics 51:526–536
2. Maiti CK (2017) Introducing technology computer-aided design (TCAD) - fundamentals, simulations, and applications. Pan Stanford Publishing Ltd., Singapore
3. Dash T P, Jena J, Mohapatra E, Dey S, Das S, Maiti C K (2019) Role of stress/strain mapping in advanced CMOS process technology nodes. IEEE international conference on device integrated circuits (DevIC-2019): 21-25
4. Pidin S, Mori T, Inoue K, Fukuta S, Itoh N, Mutoh E, Ohkoshi K, Nakamura R, Kobayashi K, Kawamura K, Saiki T, Fukuyama S, Satoh S, Kase M, Hashimoto K (2004) A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films. In IEEE Electron Devices Meeting IEDM-2004:213–216
5. Nouri F, Verheyen P, Washington L, Moroz V, De Wolf I, Kawaguchi M, Biesemans S, Schreutelkamp R, Kim Y, Shen M, Xu X, Rooyackers R, Jurczak M, Eneman G, De Meyer K, Smith L, Pramanik D, Forstner H, Thirupapuliyur S, Higashi GS (2004) A systematic study of trade-offs in engineering a locally strained pMOSFET. IEEE Electron Devices Meeting (IEDM-2004):1055–1058