Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications
Author:
Funder
University Grants Commission
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s12633-019-00280-9.pdf
Reference34 articles.
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3. Gnudi A, Reggiani S, Gnani E, Baccarani G (2013) Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Trans Electron Devices 60:1342–1348. https://doi.org/10.1109/TED.2013.2247765
4. Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Dehdashti Akhavan N et al (2010) High-temperature performance of silicon junctionless MOSFETs. IEEE Trans Electron Devices 57:620–625. https://doi.org/10.1109/TED.2009.2039093
5. Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R et al (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65–66:33–37. https://doi.org/10.1016/j.sse.2011.06.004
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