Author:
Wieler Richard W.,Zhang Zaifu,McLeod Robert D.
Publisher
Springer Berlin Heidelberg
Reference19 articles.
1. A. Krasniewski, and S. Pilarski, Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits, IEEE Transactions on Computer-Aided Design, Vol. 8, pp.425–428, Jan. 1989.
2. S. Pilarski, A. Krasniewski, and T. Kameda, Estimating Testing Effectiveness of the Circular Self-Test Path Technique, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, pp.1301–1317, Oct. 1992.
3. Algotronix Ltd., Configurable Array Logic User Manual, Edinburgh UK, 1991.
4. E. J. McClauskey, Built-in Self-Test Techniques, IEEE Design and Test of Computers, pp.21–36, April 1985.
5. P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
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