FPGAs BIST Evaluation

Author:

Parreira A.,Teixeira J. P.,Santos M. B.

Publisher

Springer Berlin Heidelberg

Reference26 articles.

1. Bushnel, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Pubs., Dordrecht (2000)

2. Stroud, C.E.: A Designer’s Guide to Built-In Self Test. Kluwer Academic Pubs., Dordrecht (2002) ISBN 1-4020-7050-0

3. Emmert, J., Baumgart, S., Kataria, P., Taylor, A., Stroud, C., Abramovici, M.: On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001 (October 2001)

4. Lecture Notes in Computer Science;M.G. Gericota,2002

5. Niermann, T.M., Cheng, W.T., Patel, J.H.: PROFS: A fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Computer-Aided Design, 198–207 (1992)

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