Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Mechanical Engineering
Reference21 articles.
1. Lancaster, A., & Keswani, M. (2018). Integrated circuit packaging review with an emphasis on 3D packaging. The VLSI Journal Integration,
60, 204–212.
2. Yew, M., & Chiang, K. (2007). A study of material effects for the panel level package (PLP) technology. In 2007 International microsystems, packaging, assembly and circuits technology (pp. 98–101).
3. Braun, T., Bechker, K. F., Voges, S., Thomas, T., Kabhle, R., Bader, V., et al. (2014). Challenges and opportunities for fan-out panel level packing (FOPLP). In 2014 9th international microsystems, packaging, assembly and circuits technology conference (pp. 154–157).
4. Kim, J., Choi, I., Park, J., Lee, J., Jeong, T., Byun, J., et al. (2018). Fan-out panel level package with fine pitch a pattern. In 2018 IEEE 68th electronic components and technology conference (pp. 52–57).
5. Tani, M., Nakagawa, K., & Mizukoshi, M. (2010). Multilayer wiring technology with grinding planarization of dielectric layer and via posts. Transactions of the Japan Institute of Electronics Packaging,
3(1), 1–6.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献