Challenges and opportunities for Fan-out Panel Level Packing (FOPLP)
Author:
Affiliation:
1. Fraunhofer Institute for Reliability and Microintegration
2. Technical University Berlin, Microperipheric Center, Gustav-Meyer-Allee 25, 13355 Berlin, Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7026493/7048336/07048374.pdf?arnumber=7048374
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Balancing the Thermal and Chemical Impact on EMC and Temporary Adhesives in Fan-Out Panel Level Packaging Process;2022 23rd International Conference on Electronic Packaging Technology (ICEPT);2022-08-10
2. Integration Strategy on Low-Cost Chip-First Fan-Out Panel Level Packaging;2022 China Semiconductor Technology International Conference (CSTIC);2022-06-20
3. A Quantitative Model to Understand the Effect of Gravity on the Warpage of Fan-Out Panel-Level Packaging;IEEE Transactions on Components, Packaging and Manufacturing Technology;2021-11
4. Comprehensive Investigation on Warpage Management of FOPLP with Multi Embedded Ring Designs;2019 IEEE 69th Electronic Components and Technology Conference (ECTC);2019-05
5. Mechanism of Moldable Underfill (MUF) Process for RDL-1^st Fan-Out Panel Level Packaging (FOPLP);2019 IEEE 69th Electronic Components and Technology Conference (ECTC);2019-05
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