Floating-Body SOI Memory: The Scaling Tournament-Reference-Cited by-同舟云学术

Floating-Body SOI Memory: The Scaling Tournament

Published:2011 Issue: Volume: Page:393-421
ISSN:1612-1317
Container-title:Semiconductor-On-Insulator Materials for Nanoelectronics Applications
language:
Short-container-title:

Author:

Bawedin M.,Cristoloveanu S.,Hubert A.,Park K. H.,Martinez F.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-15868-1_21

Reference59 articles.

1. Wann, H.J., Hu, C.: A capacitorless DRAM cell on SOI substrate. In: Electron Devices Meeting IEDM ‘93 Technical Digest International, pp. 635–638 (1993)

2. Okhonin, S., Nagoga, M., Sallese, J.M., Fazan, P.: A SOI capacitor-less 1T-DRAM concept. In: SOI Conference 2001 IEEE International, pp. 153–154 (2001)

3. Okhonin, S., Nagoga, M., Sallese, J.M., Fazan, P.: A capacitor-less 1T-DRAM cell. Electron Device Lett. IEEE 23, 85–87 (2002)

4. Hu, C., King, T.-J., Hu, C.: A capacitorless double-gate DRAM cell. Electron Device Lett. IEEE 23, 345–347 (2002)

5. Kuo, C., King, T.J., Hu, C.: A capacitorless double-gate DRAM cell design for high density applications. In: Electron Devices Meeting IEDM ‘02 Digest International, pp. 843–846 (2002)

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The SOI Transistor;75th Anniversary of the Transistor;2023-07-03

2. Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications;Solid-State Electronics;2022-07

3. A Review of Sharp-Switching Band-Modulation Devices;Micromachines;2021-12-11

4. Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications;2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS);2021-09-01

5. A2RAM compact modeling: From DC to 1T-DRAM memory operation;Solid-State Electronics;2020-06