A2RAM compact modeling: From DC to 1T-DRAM memory operation-Reference-Cited by-同舟云学术

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A2RAM compact modeling: From DC to 1T-DRAM memory operation

Published:2020-06 Issue: Volume:168 Page:107731
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Wakam F. Tcheme,Lacord J.,Bawedin M.,Martinie S.,Cristoloveanu S.,Ghibaudo G.,Barbe J.-Ch.

Funder

European Union’s

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. Zero capacitor embedded memory technology for system on chip;Okhonin,2005

2. New concepts for 1T-DRAMS: covercoming the scaling limits;Rodriguez,2011

3. Experimental demonstration of capacitorless A2RAM cells on silicon-on-insulator;Rodriguez;IEEE Electron Device Lett,2012

4. Optimization guidelines of A2RAM cell performance through TCAD simulations;Tcheme Wakam,2017

5. Evidence of fast and low-voltage A2RAM ‘1’ state programming;Tcheme Wakam,2018

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Memory Operation of Z²-FET Without Selector at High Temperature;IEEE Journal of the Electron Devices Society;2021

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