A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability-Reference-Cited by-同舟云学术

A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

Published:2016-09-29 Issue:4 Volume:94 Page:3513-3529
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Lorenzo Rohit,Chaudhury Saurabh

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://link.springer.com/article/10.1007/s11277-016-3788-5/fulltext.html

Reference22 articles.

1. Prince, B. (1991). Semiconductor memories. New York: Wiley.

2. International Technology Roadmap for Semiconductors. (2012). http://www.itrs.net/Links/2012ITRS/Home2012.htm .

3. Yamaoka, M., & Kawahara, T. (2007). Operating-margin-improved SRAM with column-at-a-time body-bias control technique. In Proceedings of the european solid-state circuits conference (ESSCIRC) (pp. 396–399).

4. Yang, Y., Park, J., Song, S. C., Wang, J., Yeap, G., & Jung, S. O. (2015). Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology. IEEE Transaction on Very Large Scale Integration, 23(11), 2748–2752.

5. Dreslinski, R. G., Wieckowski, M., Blaauw, D., Sylvester, D., & Mudge, T. (2010). Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. Proceedings IEEE, 98(2), 253–266.

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