Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET)
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s11664-024-10997-y.pdf
Reference36 articles.
1. A. Ionescu and H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). https://doi.org/10.1038/nature10679.
2. N. Bagga, A. Kumar, and S. Dasgupta, Demonstration of a novel two source region tunnel FET. IEEE Trans. Electron Devices 64(12), 5256–5262 (2017). https://doi.org/10.1109/TED.2017.2759898.
3. Dharmender and K. Nigam, Low-K dielectric pocket and workfunction engineering for DC and analog/RF performance improvement in dual material stack gate oxide double gate TFET. SILICON 13, 2347–2356 (2021). https://doi.org/10.1007/s12633-020-00822-6.
4. P. Verma, K. Nigam, and S. Kumar, Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET. Appl. Phys. A 128, 955 (2022). https://doi.org/10.1007/s00339-022-06083-x.
5. R. Saha, R. Goswami, and D.K. Panda, Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET. Microelectron. J. 130, 105629 (2022). https://doi.org/10.1016/j.mejo.2022.105629.
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