Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic-Reference-Cited by-同舟云学术

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

Published:2021-03-05 Issue:5 Volume:50 Page:2618-2629
ISSN:0361-5235
Container-title:Journal of Electronic Materials
language:en
Short-container-title:Journal of Elec Materi

Author:

Jain F.,Saman B.,Gudlavalleti R.,Mays R.,Chandy J.,Heller E.

Funder

National Science Foundation

Office of Naval Research

Publisher

Springer Science and Business Media LLC

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1007/s11664-021-08807-w.pdf

Reference21 articles.

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2. S. Karmakar, E. Suarez, M. Gogna, and F. Jain, J. Electron. Mater. 41(10), 2663 (2012).

3. M. Lingalugari, P. Mirdha, J. Chandy, E. Heller, and F. Jain, Electron. Lett. 54, 36 (2018).

4. B. Saman, P. Gogna, E.-S. Hasaneen, J. Chandy, E. Heller, and F.C. Jain, Int. J. High Speed Electron. Syst. 26, 1740009 (2017).

5. S. Hajare and P. Dakhole, Int. J. VLSI Des. Commun. Syst. (VLSICS) 8, 4 (2017).

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