A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition-Reference-Cited by-同舟云学术

A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

Published:2019-07-25 Issue:5 Volume:17 Page:1421-1446
ISSN:1861-8200
Container-title:Journal of Real-Time Image Processing
language:en
Short-container-title:J Real-Time Image Proc

Author:

Chakraborty Anirban,Banerjee Ayan

Publisher

Springer Science and Business Media LLC

Subject

Information Systems

Link

http://link.springer.com/content/pdf/10.1007/s11554-019-00901-x.pdf

Reference26 articles.

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4. Mohanty, B.K., Meher, P.K.: Efficient multiplierless designs for 1-D DWT using 9/7 filters based on distributed arithmetic. In: Proceedings of the 2009 12th International Symposium on Integrated Circuits, Singapore, pp. 364–367 (2009)

5. Mahajan, A., Mohanty, B.K.: Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic. In: IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, pp. 1195–1198 (2010)

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