Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic-Reference-Cited by-同舟云学术

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Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic

Published:2010-12 Issue: Volume: Page:
ISSN:
Container-title:2010 IEEE Asia Pacific Conference on Circuits and Systems
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Author:

Mahajan Anurag,Mohanty Basant K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5767825/5774732/05775015.pdf?arnumber=5775015

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Review of Hardware Implementations of Convolution for Discrete Wavelet Transform;2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon);2022-11-20

2. A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic;Journal of Circuits, Systems and Computers;2020-02-05

3. A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition;Journal of Real-Time Image Processing;2019-07-25

4. Very large‐scale integration architecture for wavelet‐based ECG signal adaptive coder;IET Signal Processing;2019-02

5. Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters;2015 28th International Conference on VLSI Design;2015-01

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