Review of Hardware Implementations of Convolution for Discrete Wavelet Transform-Reference-Cited by-同舟云学术

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Review of Hardware Implementations of Convolution for Discrete Wavelet Transform

Published:2022-11-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon)
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Author:

C Ramprakash¹,Prasad Skanda¹,R Pratyusha¹,Jayaramu Raghu¹

Affiliation:

1. The National Institute of Engineering,Department of Electronics and Communication Engineering,Mysuru,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10126138/10126139/10126593.pdf?arnumber=10126593

Reference11 articles.

1. A faster distributed arithmetic architecture for FPGAs

2. An Efficient 256-Tap Parallel FIR Digital Filter Implementation Using Distributed Arithmetic Architecture

3. Distributed Arithmetic for FIR Filter implementation on FPGA

4. Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic

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