A faster distributed arithmetic architecture for FPGAs
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ACM Press
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Modeling and simulation of FIR filter using distributed arithmetic algorithm on FPGA;Multimedia Tools and Applications;2024-02-20
2. Review of Hardware Implementations of Convolution for Discrete Wavelet Transform;2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon);2022-11-20
3. Efficient Architecture for the Realization of 2-D Adaptive FIR Filter Using Distributed Arithmetic;Circuits, Systems, and Signal Processing;2020-09-18
4. ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic;Circuits, Systems, and Signal Processing;2017-11-07
5. POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters;Journal of Signal Processing Systems;2012-02-29
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