Author:
Bouwens Frank,Berekovic Mladen,Kanstein Andreas,Gaydadjiev Georgi
Publisher
Springer Berlin Heidelberg
Reference10 articles.
1. Mei, B., et al.: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In: DATE 2004, Leuven, Belgium, IMEC (2004)
2. Kwok, Z., Wilton, S.J.E.: Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. In: Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’05), University of British Columbia, April 2005, pp. 35–44. IEEE Computer Society Press, Los Alamitos (2005)
3. The IMPACT Group. http://www.crhc.uiuc.edu/Impact/
4. http://www-sop.inria.fr/esterel-org/
5. http://www.synopsys.com/
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