Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC-Reference-Cited by-同舟云学术

Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC

Published:2023-05 Issue: Volume: Page:
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Container-title:2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
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Author:

Adhi Boma¹,Cortes Carlos¹,Sozzo Emanuele Del¹,Ueno Tomohiro¹,Tan Yiyu²,Kojima Takuya³,Podobas Artur⁴,Sano Kentaro¹

Affiliation:

1. Center for Computational Science (R-CCS), RIKEN,Japan

2. Iwate University,Faculty of Science and Engineering,Japan

3. The University of Tokyo,Graduate School of Information Science and Technology,Japan

4. KTH Royal Institute of Technology,Sweden

Funder

Technology Development

Ministry of Education

Japan Society for the Promotion of Science

Publisher

IEEE

Link

Reference23 articles.

5. An architecture-agnostic integer linear programming approach to cgra mapping;chin;Proceedings of the 55th Annual Design Automation Conference,2018

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3. TransMap: An Efficient CGRA Mapping Framework via Transformer and Deep Reinforcement Learning;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27