ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix-Reference-Cited by-同舟云学术

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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Published:2003 Issue: Volume: Page:61-70
ISSN:0302-9743
Container-title:Field Programmable Logic and Application
language:
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Author:

Mei Bingfeng,Vernalde Serge,Verkest Diederik,De Man Hugo,Lauwereins Rudy

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-45234-8_7

Reference13 articles.

1. Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Filho, E.M.C.: Morphosys: an integrated reconfigurable system for data-parallel and computationintensive applications. IEEE Trans. on Computers 49, 465–481 (2000)

2. Lecture Notes in Computer Science;C. Ebeling,1996

3. Chameleon Systems Inc. (2002), http://www.chameleonsystems.com

4. Miyamori, T., Olukotun, K.: REMARC: Reconfigurable multimedia array coprocessor. In: FPGA, p. 261 (1998)

5. Patterson, D.A., Hennessy, J.L.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., San Francisco (1996)

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