An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits
Author:
Funder
National Natural Science Foundation of China
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-020-05891-4.pdf
Reference19 articles.
1. Tang D, Li YH, Zhang GH, He CH, Fan YY (2013) Single event upset sensitivity of 45nm FDSOI and SOI FinFET SRAM. SCIENCE CHINA Technol Sci 56(3):780–785. https://doi.org/10.1007/s11431-012-5125-x
2. Calomarde A, Amat E, Moll F, Vigara J, Rubio A (2014) SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET. Microelectron Reliab 54:738–745. https://doi.org/10.1016/j.microrel.2013.12.018
3. Scholz M, Chen SH, Hellings G, Linten D (2016) Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC. Microelectron Reliab 57:53–58. https://doi.org/10.1016/j.microrel.2015.12.009
4. Wirth GI, Vieira MG, Neto EH, Kastensmidt FL (2008) Modeling the sensitivity of CMOS circuits to radiation induced single event transients. Microelectron Reliab 48:29–36. https://doi.org/10.1016/j.microrel.2007.01.085
5. Sayil S, Boorla VK, Reddula SR (2011) Modeling single event crosstalk in nanometer technologies. IEEE Trans Nucl Sci 58(5):2493–2502. https://doi.org/10.1109/TNS.2011.2165295
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