SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Author:

Calomarde A.,Amat E.,Moll F.,Vigara J.,Rubio A.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference37 articles.

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5. http://www.eetimes.com/electronicsnews/4213622/TSMC-to make-FinFETs-in 450-mm-fab.

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4. General Trade-Offs;Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs;2021

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