General Trade-Offs
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-68368-9_8
Reference4 articles.
1. Alghareb, F.S., Ashraf, R.A., Alzahrani, A., DeMara, R.F.: Energy and delay tradeoffs of soft-error masking for 16-nm FinFET logic paths: survey and impact of process variation in the near-threshold region. IEEE Trans. Circuits Syst. II: Express Briefs 64(6), 695–699 (2017)
2. Brendler, L.H., Zimpeck, A.L., Meinhardt, C., Reis, R.: Exploring multi-level design to mitigate variability and radiation effects on 7nm FinFET logic cells. In: 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 581–584 (2018)
3. Calomarde, A., Amat, E., Moll, F., Vigara, J., Rubio, A.: Set and noise fault tolerant circuit design techniques: Application to 7nm FinFET. Microelectron. Reliab. 54(4), 738–745 (2014)
4. Moraes, L., Zimpeck, A., Meinhardt, C., Reis, R.: Evaluation of variability using schmitt trigger on full adders layout. Microelectron. Reliab. 88–90, 116–121 (2018). 29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis ( ESREF 2018 )
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