Author:
Wu Meng-Fan,Hu Kai-Shun,Huang Jiun-Lang
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference38 articles.
1. Ahmed N, Tehranipoor M, Jayaram V (2007) Supply voltage noise aware ATPG for transition delay faults. In: Proc. VLSI test symposium, pp 179–186
2. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr Syst 13(3):384–395
3. Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2001) A gated clock scheme for low power scan testing of logic ICs or embedded cores. In: Proc. asian test symposium, pp 253–258
4. Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2002) Power driven chaining of flip-flops in scan architectures. In: Proc. international test conference, pp 796–803
5. Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2003) Efficient scan chain design for power minimization during scan testing under routing constraint. In: Proc. international test conference, pp 488–493
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献