TSV-to-TSV Coupling Analysis and Optimization
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Published:2012-09-24
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Page:189-203
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ISSN:
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Container-title:Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
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language:
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Publisher
Springer New York
Reference9 articles.
1. D.H. Kim, K. Athikulwongse, S.K. Lim, A study of through-silicon-via impact on the 3D stacked IC layout, in Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, 2009 2. J. Kim, E. Song, J. Cho, J.S. Pak, J. Lee, H. Lee, K. Park, J. Kim, Through silicon via (TSV) equalizer, in Proceedings of the IEEE Electrical Performance of Electronic Packaging, Portland, 2009 3. Y.-J. Lee, S.K. Lim, Timing analysis and optimization for 3D stacked multi-core microprocessors, in IEEE International 3D System Integration Conference, Münich, 2010 4. C. Liu, T. Song, J. Cho, J. Kim, J. Kim, S.K. Lim, Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC, in Proceedings of the ACM Design Automation Conference, San Diego, 2011 5. M. Pathak, Y.-J. Lee, T. Moon, S.K. Lim, Through-silicon-via management during 3D physical design: when to add and how many? in Proceedings of the IEEE International Conference on Computer-Aided Design, San Jose, 2010
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