Interconnect Processing: Integration, Dielectrics, Metals
Author:
Chen Shyng-Tsong,Lanzillo Nicholas A.,Van Nguyen Son,Nogami Takeshi,Simon Andrew H.
Publisher
Springer International Publishing
Reference172 articles.
1. Edelstein, D.C.: On-Chip ULSI Interconnect Technology, its Extendibility, and Integrated Devices. Columbia University Short Course (2017) 2. Chen, S.-T., Tomizawa, K., Tsumura, M., Tagami, H., Shobha, M., Van Sankarapandian, O., der Straten, J., Kelly, D., Canaperi, T., Levin, S., Cohen, Y., Yin, D., Horak, M., Ishikawa, Y., Mignot, C.-S., Koay, S., Burns, S., Halle, H., Kato, G., Landie, Y., Xu, A., Scaduto, E., Mclellan, J.C., Arnold, M., Colburn, T., Usui, T.: Spooner, 64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme. In: 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM, vol. 2011, pp. 1–3 (2011). https://doi.org/10.1109/IITC.2011.5940273 3. Burkhardt, M., Arnold, J.C., Baum, Z., Burns, S., Chang, J., Chen, J., Cho, J., Dai, V., Deng, Y., Halle, S., Han, G., Holmes, S., Horak, D., Kanakasabapathy, S., Kim, R.H., Klatchko, A., Koay, C.S., Krasnoperova, A., Ma, Y., McLellan, E., Petrillo, K., Schmitz, S., Tabery, C., Yin, Y., Zhuang, L., Zou, Y., Kye, J., Paruchuri, V., Mansfield, S., Spence, C., Colburn, M.: Overcoming the challenges of 22-nm node patterning through litho-design co-optimization. In: Proc. SPIE 7274, Optical Microlithography XXII, 727404 (2009). https:/978-3-030-79827-7/doi.org/10.1117/12.814433 4. Holmes, S.J., Tang, C., Arnold, J.C., Yin, Y., Chen, R., Fender, N., Osborn, B., Dabbagh, G., Liu, S., Colburn, M., Varanasi, R.P., Slezak, M.: Process characterization of pitch-split resist materials for application at 16nm node. In: Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 76392X (2010). https://doi.org/10.1117/12.846891 5. Koay, C.-S., Holmes, S., Petrillo, K., Colburn, M., Burns, S., Dunn, S., Cantone, J., Hetzer, D., Kawakami, S., van Dommelen, Y., Jiang, A., Many, M., Routh, R., Huli, L., Martinick, B., Rodgers, M., Tomizawa, H., Kini, S.: Evaluation of double-patterning techniques for advanced logic nodes. In: Proc. SPIE 7640, Optical Microlithography XXIII, 764009 (2010). https://doi.org/10.1117/12.846769
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