Compile time instruction cache optimizations-Reference-Cited by-同舟云学术

Compile time instruction cache optimizations

Published:1994 Issue: Volume: Page:404-418
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Mendlson Abraham,Pinter Shlomit S.,Shtokhamer Ruth

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-57877-3_27

Reference13 articles.

1. A. V. Aho, R. Sethi, and J. D. Ullman. Compilers — Principles, Techniques, and Tools. Addison-Wesley, Reading, MA, 1986.

2. D. Bernstein, D. Cohen, Y. Lavon, and V. Rainish. Performance evaluation of instruction scheduling on the IBM RISC system/6000. In 25th Annual International Symposium on Microarchitecture, pages 226–235, Portland, Oregon, December 1992.

3. C. Chi-Hung and H. Dietz. Improving cache performance by selective cache bypass. Hawaii International Conference on System Science, pages 277–285, 1989.

4. R. Gupta and C. Chi-Hung. Improving instruction cache behavior by reducing cache pollution. In Proc. of Supercomputing '90, pages 82–91, New-York, November 1990.

5. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Kaufman, 1990.

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