Performance evaluation of instruction scheduling on the IBM RISC System/6000-Reference-Cited by-同舟云学术

Performance evaluation of instruction scheduling on the IBM RISC System/6000

Published:1992-12-10 Issue:1-2 Volume:23 Page:226-235
ISSN:1050-916X
Container-title:ACM SIGMICRO Newsletter
language:en
Short-container-title:SIGMICRO Newsl.

Author:

Bernstein David,Cohen Doron,Lavon Yuval,Rainish Vladimir

Publisher

Association for Computing Machinery (ACM)

Reference25 articles.

1. D. Bernstein and I. Gertner. Scheduling expressions on a pipelined processor with a maxima} delay of one cycle. A CM Transactions on Pro#ramming Languages and Systems 11(1):57-66 1989. 10.1145/59287.59291 D. Bernstein and I. Gertner. Scheduling expressions on a pipelined processor with a maxima} delay of one cycle. A CM Transactions on Pro#ramming Languages and Systems 11(1):57-66 1989. 10.1145/59287.59291

2. Global instruction scheduling for superscalar machines

3. P.P. Chang S.A. Mahlke W.Y. Chen N.J. Warter and W.W. Hwu. IMPACT: An architectural framework for multiple-issue processors. In IEEE Con/erence on Computer Architecture pages 266-275 1991. 10.1145/115952.115979 P.P. Chang S.A. Mahlke W.Y. Chen N.J. Warter and W.W. Hwu. IMPACT: An architectural framework for multiple-issue processors. In IEEE Con/erence on Computer Architecture pages 266-275 1991. 10.1145/115952.115979

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