Advances in the Fabrication Processes and Applications of Wafer Level Packaging

Author:

Liu Peisheng12,Wang Jinlan3,Tong Liangyu4,Tao Yujuan5

Affiliation:

1. Jiangsu Key Laboratory of ASIC Design, Nantong University, Nantong 226019, China;

2. Nantong Fujistu Microelectronics Co., Ltd, Nantong 226006, China e-mail:  and

3. Nantong University, Nantong 226019, China

4. Jiangsu Key Laboratory of ASIC Design, Nantong University, Nantong 226019, China

5. Nantong Fujistu Microelectronics Co., Ltd., Nantong 226006, China

Abstract

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

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