Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

Author:

Xi Jia1,Zhai Xinduo1,Wang Jun1,Yang Donglun1,Ru Mao1,Xiao Fei2,Zhang Li3,Ming Lai Chi3

Affiliation:

1. Department of Materials Science, Fudan University, Shanghai 200433, China

2. Department of Materials Science, Fudan University, Shanghai 200433, China e-mail:

3. Jiangyin Changdian Advanced Packaging Co., Ltd., Jiangyin 214431, China

Abstract

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference20 articles.

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4. Xu, S., Keser, B., Hau-Riege, C., Bezuk, S., and Yau, Y. W., 2013, “A Study of Wafer Level Package Board Level Reliability,” IEEE 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, NV, May 28–31, pp. 1204–1209.http://dx.doi.org/10.1109/ECTC.2013.6575728

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