Simulations of Process-Induced Warpage During IC Encapsulation Process

Abstract

Warpage during integrated circuit encapsulation process is a serious problem. Previous researchers had focused on warpage analysis with thermal-induced shrinkage and the cure-induced shrinkage was neglected. A new approach considering both cure- and thermal-induced shrinkage during encapsulation process was presented to predict the amount of warpage. The cure-induced shrinkage was described by the pressure-volume-temperature-cure (P-V-T-C) equation of epoxy. The thermal-induced shrinkage was described by the coefficients of thermal expansion of the component materials. The thin small outline package (TSOP) DBS-27P and low-profile quad flat package (LQFP) LQFP-64, which were manufactured by Philips Semiconductor located in Taiwan and Siliconware Precision Industries Corporation, respectively, were chosen to be the simulation models. By comparing the amount of predicted warpage with the experimental results, it showed that the approach could better predict the amount of warpage than that considering only thermal-induced shrinkage. It was also found that the sign of cure-induced warpage could be opposite to the thermal-induced warpage. Appropriate design of a package to make cure- and thermal-induced shrinkage to be of opposite sign could minimize the warpage of a package.