Constrained Three-Dimensional Component Layout Using Simulated Annealing-Reference-Cited by-同舟云学术

Constrained Three-Dimensional Component Layout Using Simulated Annealing

Published:1997-03-01 Issue:1 Volume:119 Page:28-35
ISSN:1050-0472
Container-title:Journal of Mechanical Design
language:en
Short-container-title:

Author:

Szykman S.¹,Cagan J.²

Affiliation:

1. Engineering Design Laboratory, Manufacturing Systems Integration Division, National Institute of Standards and Technology, Gaithersburg, MD 20899

2. Department of Mechanical Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract

This research introduces a computational algorithm that uses simulated annealing to optimize three-dimensional component layouts. General component layout problems are characterized by three objectives: achieving high packing density, fitting components into a given container and satisfying spatial constraints on components. This paper focuses on the extension of a simulated annealing packing algorithm to a general layout algorithm through the implementation of a language of spatial constraints that are characteristic of layout problems. These constraints allow the designer to specify desired component proximities or to restrict translation or rotation of components based on a global origin or set of coordinate axes, or relative to other component locations or orientations. The layout of components from a cordless power drill illustrates the algorithm.

Publisher

ASME International

Subject

Computer Graphics and Computer-Aided Design,Computer Science Applications,Mechanical Engineering,Mechanics of Materials

Link

http://asmedigitalcollection.asme.org/mechanicaldesign/article-pdf/119/1/28/5527922/28_1.pdf

Reference18 articles.

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2. Coffman, E. G., Jr., Garey, M. R., and Johnson, D. S., 1984, “Approximation Algorithms for Bin-Packing—An Updated Survey,” Algorithm Design for Computer System Design, G. Ausiello, M. Lucertini and P. Serafini, eds., Springer-Verlag, New York, pp. 49–106.

3. Cohn J. M. , GarrodD. J., RutenbarR. A., and CarleyL. R., 1991, “KOAN/ANGRAM II: New Tools for Device-Level Analog Placement and Routing,” IEEE Journal of Solid-State Circuits, Vol. 23, pp. 330–342.

4. Dowsland K. A. , and DowslandW. B., 1992, “Packing Problems,” European Journal of Operational Research, Vol. 56, pp. 2–14.

5. Dyckhoff H. , 1990, “A Typology of Cutting and Packing Problems,” European Journal of Operational Research, Vol. 44, pp. 145–159.

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