FEM Analysis on Mechanical Stress of 2.5D Package Interposers

Author:

Hisada Takashi,Aoki Toyohiro,Asai Junko,Yamada Yasuharu

Publisher

Japan Institute of Electronics Packaging

Reference12 articles.

1. [1] J. U. Knickerbocker et al., "Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection," IBM J. Res. Dev., Vol. 49, No. 4/5, pp. 725-753, Jul/Sep. 2005.

2. [2] J. U. Knickerbocker et al., "3-D silicon integration," Proceedings of the 2008 Electronic Components and Technology Conference, pp. 538-543, 2008.

3. [3] JESD229, "Wide I/O Single Data Rate (Wide I/O SDR)," JEDEC Standard, 2011.

4. [4] MO-305A, "Wide I/O Micropillar Grid Array Package (MPGA)," JEDEC Solid State Product outline, 2011.

5. [5] K. Kumagai et al., "A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection," Proceedings of the 2008 Electronic Components and Technology Conference, pp. 571-576, 2008.

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