Evaluation of Residual Stress and Warpage of Device Embedded Substrates with Piezo-Resistive Sensor Silicon Chips

Author:

Han Younggun1,Horiuchi Osamu1,Hayashi Shigehiro2,Nogita Kanta2,Katoh Yoshihisa1,Nanami Kyosuke3,Tomokage Hajime123

Affiliation:

1. Center of System Integration Platform Organization Standards, Fukuoka University

2. Research Center for Three Dimensional Semiconductors

3. Department of Electronics Engineering & Computer Science, Fukuoka University

Publisher

Japan Institute of Electronics Packaging

Reference21 articles.

1. [1] A. Ostmann, D. Manessis, J. Stahr, M. Beesley, M. Cauwe, and J. D. Baets, "Industrial and Technical Aspects of Chip Embedding Technology," 2nd Electronics System-integration Technology Conference (ESTC), Greenwich, UK, Sept. 2008, pp. 315-320.

2. [2] G. J. Vandentop, S. N. Towle, H. Braunisch, C. Hu, and R. D. Emery, "Bumpless Build-Up Packaging," ASME International Mechanical Engineering Congress and Exposition, Nov. 2001.

3. [3] H. Braunisch, S. N. Towle, R. D. Emery, C. Hu, and G. J. Vandentop, "Electrical Performance of Bumpless Build-Up Layer Packaging," 52nd Electronic Components and Technology Conference (ECTC), May. 2002, pp. 353-358.

4. [4] T. Waris, R. Touminen, J. Kivilahti, "Panel-sized integrated module board manufacturing," Proc. Polytronics Conference, Potszam, Germany, Oct. 2001, pp. 218-223.

5. [5] A. Ostamann, A. Neumann, P. Sommer, H. Reichl, "Buried components in printed circuit boards," Advancing Microelectronics, May/Jun. 2005, pp. 13-18.

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