Author:
Konishi Tomoaki,Yotsuyanagi Hiroyuki,Hashizume Masaki
Publisher
Japan Institute of Electronics Packaging
Reference14 articles.
1. [1] V. F. Pavlidis and E. G. Friedman, "Three-dimensional Integrated Circuit Design," Morgan Kaufman, Burlington, MA, USA, 2009.
2. [2] E. J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias," Proc. of IEEE International Test Conference 2009, Paper ET1.1, pp. 1-11, 2009.
3. [3] P. Y. Chen, C. W. Wu, and D. M. Kwai, "On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding," Proc. of 2010 28th IEEE VLSI Test Symposium, pp. 263-268, 2010.
4. [4] H. Bleeker and P. van den Eijnden, "Boundary-Scan Test - A Practical Approach," Kluwer Academic Publishers, Dordrecht, The Netherlands, 1993.
5. [5] C. W. Chou, J. F. Li, J. J. Chen, D. M. Kwai, Y. F. Chou, and C. W. Wu, "A Test Integration Methodology for 3D Integrated Circuits," Proc. of 2010 19th IEEE Asian Test, pp. 377-382, 2010.
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