Electrical Interconnect Test of Solder Joint Part with Boundary Scan Flip Flops and a Built-in Test Circuit
Author:
Affiliation:
1. Tokushima University
2. National Taiwan University of Science and Technology
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/jiep/19/3/19_161/_pdf
Reference1 articles.
1. 13) J. Lee, W. Hong, and H. Chang: “A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection,” Computational Science And Its Applications - ICCSA 2006, No. 3983, pp. 577-583, 2006
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1. Testing of Weak Open Defects in Interconnects Using Boundary Scan;Journal of The Japan Institute of Electronics Packaging;2024-07-01
2. Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects;Journal of The Japan Institute of Electronics Packaging;2023-03-01
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