A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/11751632_63.pdf
Reference8 articles.
1. IEEE Std. 1149.1-2001, Test Access Port and Boundary Scan Architecture, IEEE (2001)
2. Kautz, W.H.: Testing of Faults in Wiring Interconnects. IEEE Trans. Computers 23(4) (1974)
3. Goel, P., Mcmahon, M.T.: Electronic Chip-in-Place Test. In: Proc. Int’l Test Conf. (1982)
4. de Sousa, J.T., Cheung, P.Y.K.: Boundary Scan Interconnect Diagnosis. Kluwer Academic, Dordrecht (2001)
5. Park, S., Kim, T.: A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. In: Design, Automation and Test in Europe Conf. (2000)
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Electrical Interconnect Test of Solder Joint Part with Boundary Scan Flip Flops and a Built-in Test Circuit;Journal of Japan Institute of Electronics Packaging;2016
2. 10.5104/jiep.14.99;Journal of Japan Institute of Electronics Packaging;2011
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