3D Stacking Process Technologies for Advanced CMOS Image Sensors
Author:
Affiliation:
1. Sony Semiconductor Solutions Corporation
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/jiep/27/1/27_163/_pdf
Reference11 articles.
1. 1) S. Iwabuchi, et al.: "A back-illuminated high-sensitivity small-pixel color CMOS image sensor with flexible layout of metal wiring," ISSCC 2006
2. 2) ソニーの裏面照射型CMOSセンサー工場を訪ねる,https://dc.watch.impress.co.jp/docs/review/special/351111.html
3. 3) S. Sukegawa, et al.: "A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
4. 4) T. Umebayashi, et al.: "3D Stacked CMOS Image Sensor Exmor RSTM," ISSCC Advance Program, 2014
5. 5) Y. Oike: "Evolution of Image Sensor Architectures with Stacked Device Technologies," IEICE ESS Fundamentals Review, Vol. 15, Issue 1, 2021
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1. Present, Past, and Future of 3D Integration;Journal of The Japan Institute of Electronics Packaging;2024-03-01
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