Product Yield Test and Diagnostics

Author:

Pan Yan1,Estores Rommel2

Affiliation:

1. Microsoft Corporation

2. Onsemi

Abstract

Abstract A typical mobile processor die may contain, among other things, a variety of high-performance as well as low-power processing cores along with 5G modems, Wi-Fi modules, image processors, GPUs, and security modules, with a total transistor count exceeding 10 billion. Such designs pose many challenges for yield ramp and diagnostics. This chapter examines these challenges and the growing demand for innovative solutions to help failure analysts quickly and accurately isolate faults. It also assesses the capabilities and future potential of ATPG scan diagnostics, streaming scan networks, and advanced fault models for diagnosing embedded memory.

Publisher

ASM International

Reference21 articles.

1. Failure Diagnosis of Structured VLSI;Waicukauski;Proc. of IEEE Design and Test of Computers,1989

2. Diagnosing Combinational Logic Designs using the Single Location At A Time (SLAT) Paradigm;Bartenstein;Proc. of Intl. Test Conf.,2001

3. Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns;Huang;Proc. of Asian Test Symp.,2009

4. Experiences with Layout-Aware Diagnosis—A Case Study;Chang;Electronic Device Failure Analysis,2010

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