STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application-Reference-Cited by-同舟云学术

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STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application

Published:2021-05 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Memory Workshop (IMW)
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Author:

Rao S.,Kim W.,van Beek S.,Kundu S.,Perumkunnil M.,Cosemans S.,Yasin F.,Couet S.,Carpenter R.,O'Sullivan B.J.,Sharifi S. H.,Jossart N.,Souriau L.,Goux L.,Crotti D.,Kar G. S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9439548/9439588/09439592.pdf?arnumber=9439592

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications;Journal of Semiconductors;2023-12-01

2. Distributions of easy axes and reversal processes in patterned MRAM arrays;Scientific Reports;2023-11-22

3. Device Aware Diagnosis for Unique Defects in STT-MRAMs;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14

4. STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes;ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC);2023-09-11

5. Magnetic Domain Wall Memory: A DTCO study for Memory Applications;ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC);2023-09-11

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